SY100ELT22 translator equivalent, dual ttl-to-differential pecl translator.
* 300 ps Typical Propagation Delay
* <100 ps Output-to-Output Skew
* Differential PECL Outputs
* PNP TTL Inputs for Minimal Loading
* Flow-Through Pin.
that require the translation of a clock and a data signal.
The SY100ELT22 is compatible with positive ECL 100K logic lev.
The SY100ELT22 is a dual TTL-to-differential PECL translator. Because positive ECL (PECL) levels are used, only +5V and ground is required. The small outline 8-lead SOIC package and the low-skew, dual-gate design of the SY100ELT22 makes it ideal for .
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