SY100ELT23 translator equivalent, dual differential pecl-to-ttl translator.
s 3.0ns typical propagation delay s <500ps typical output-to-output skew s Differential PECL inputs s 24mA TTL outputs s Flow-through pinouts s Internal input 50kΩ pulldo.
which require the translation of a clock and a data signal.
The ELT23 is available in both ECL standards: the 10ELT is c.
The SY10/100ELT23 are dual differential PECL-to-TTL translators. Because PECL (Positive ECL) levels are used, only +5V and ground are required. The small outline 8-lead SOIC package and the low skew dual gate design of the ELT23 makes it ideal for ap.
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