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IS61DDPB21M36A1 - 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

Download the IS61DDPB21M36A1 datasheet PDF. This datasheet also covers the IS61DDPB22M18A variant, as both devices belong to the same 36mb ddr-iip(burst 2) cio synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Common I/O read and write ports.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61DDPB22M18A-IntegratedSiliconSolution.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDPB22M36C 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDPB22M36C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDPB22M36C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDPB24M18C 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM ISSI
IS61DDPB24M18C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDPB21M36A 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M36A2 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M36B 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M36B1 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M36B2 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61DDPB22M18A/A1/A2 IS61DDPB21M36A/A1/A2 2Mx18, 1Mx36 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) ADVANCED INFORMATION JULY 2012 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
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