IS61DDPB21M36B2 Datasheet PDF (36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM) | Download Integrated Silicon Solution IS61DDPB21M36B2

IS61DDPB21M36B2 - 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61DDPB21M36B2, a member of the IS61DDPB22M18B 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM family.

Datasheet Summary

Description

1Mx36 and 2Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Common I/O read and write ports.

Synchronous pipeline read with self-timed late write operation.

Double Data Rate (DDR) interface for read and write input ports.

Datasheet Details

Part number	IS61DDPB21M36B2
Manufacturer	Integrated Silicon Solution
File Size	696.45 KB
Description	36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
Datasheet	IS61DDPB21M36B2 Datasheet
Additional preview pages of the IS61DDPB21M36B2 datasheet.

📁 Similar Datasheet

IS61DDPB22M36C - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDPB22M36C1 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDPB22M36C2 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDPB24M18C - 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (ISSI)

IS61DDPB24M18C1 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDPB24M18C2 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B21M36C - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B21M36C1 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B21M36C2 - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

IS61DDP2B22M18C - 36Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)

Full PDF Text Transcription

Click to expand full text

IS61DDPB22M18B/B1/B2 IS61DDPB21M36B/B1/B2 2Mx18, 1Mx36 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (2.5 Cycle Read Latency) SEPTEMBER 2014 FEATURES DESCRIPTION  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Common I/O read and write ports.  Synchronous pipeline read with self-timed late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.5 cycle read latency.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

Published: Jul 25, 2016 |