IS61DDB44M18 srams equivalent, ddr-ii (burst of 4) cio synchronous srams.
* 2M x 36 or 4M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with la.
The 72Mb IS61DDB42M36 and IS61DDB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations ar.
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