IS61DDB41M36 Datasheet, Integrated Silicon Solution

* 1M x 36 or 2M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with la.

The 36Mb IS61DDB41M36 and IS61DDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations ar.