IS61DDB41M18A sram equivalent, 18mb ddr-ii (burst 4) cio synchronous sram.
DESCRIPTION
* 512Kx36 and 1Mx18 configuration available.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common I/O read and write ports.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
* 512Kx36 and 1Mx18 configuration available.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with late write operation.
* Double Data Rate (DDR) interfa.
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