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Integrated Device Technology Electronic Components Datasheet

IDT71V67802 Datasheet

3.3V Synchronous SRAMs

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256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
IDT71V67602
IDT71V67802
Features
256K x 36, 512K x 18 memory configurations
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (VDDQ)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
Description
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
addressandcontrolregisters. InternallogicallowstheSRAMtogenerate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67602/7802 can provide four cycles of
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
datawillbeavailabletotheuseronthenextthreerisingclockedges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V67602/7802 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE Chip Enable
CS0, CS1
Chip Selects
OE Output Enable
GW Global Write Enable
BWE Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK Clock
ADV Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO Linear / Interleaved Burst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V67802.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5311 tbl 01
©2002 Integrated Device Technology, Inc.
1
FEBRUARY 2009
DSC-5311/09


Integrated Device Technology Electronic Components Datasheet

IDT71V67802 Datasheet

3.3V Synchronous SRAMs

No Preview Available !

IDT71V67602, IDT71V67802, 256K x 36, 512K x 18, 3.3V Synchronous
SRAMs with 2.5V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O Active
Description
A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSP
Address Status
(Processor)
I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the
Advance
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
CE
Chip Enable
I LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V67602/7802.
CE also gates ADSP.
CLK
Clock
I N/A This is the clock input. All timing references for the device are made with respect to this
input.
CS0
Chip Select 0
I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
Enable
on the rising edge of CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Line ar burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE
Output Enable
I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
impedance state.
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Power Supply N/A N/A 2.5V I/O Supply.
VSS
Ground
N/A N/A Ground.
NC
No Connect
N/A N/A NC pins are not electrically connected to the device.
ZZ
Sleep Mode
I HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67602/7802 to its lowest p ower consumption level. Data retention is guaranteed in
Sleep Mode.
5311 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422


Part Number IDT71V67802
Description 3.3V Synchronous SRAMs
Maker Integrated Device Technology
Total Page 23 Pages
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