IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK and ADSC Low or ADSP Low and CE Low.
LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
Byte Write Enable
LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc.
Any active byte write causes all outputs to be disabled.
I LOW Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V67603/7803.
CE also gates ADSP.
I N/A This is the clock input. All timing references for the device are made with respect to this
Chip Select 0
I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
Chip Select 1
I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW
on the rising edge of CLK. GW supersedes individual byte write enables.
N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
Linear Burst Order
LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-
VDD Power Supply N/A N/A 3.3V core power supply.
VDDQ Power Supply N/A N/A 3.3V I/O Supply.
N/A N/A Ground.
N/A N/A NC pins are not electrically connected to the device.
I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V67603/7803 to its lowest p ower consumption level. Data retention is guaranteed in
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5310 tbl 02