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IDT71V67803 - 3.3V Synchronous SRAMs

Download the IDT71V67803 datasheet PDF. This datasheet also covers the IDT71V67603 variant, as both devices belong to the same 3.3v synchronous srams family and are provided as variant models within a single manufacturer datasheet.

Description

256K x 36/512K x 18.

The IDT71V67603/7803 SRAMs contain write, data, address and control registers.

Features

  • 256K x 36, 512K x 18 memory configurations.
  • Supports high system speed:.
  • 166MHz 3.5ns clock access time.
  • 150MHz 3.8ns clock access time.
  • 133MHz 4.2ns clock access time.
  • LBO input selects interleaved or linear burst mode.
  • Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx).
  • 3.3V core power supply.
  • Power down controlled by ZZ input.
  • 3.3V I/O supply (VDDQ).
  • Packaged in a JEDEC Stand.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT71V67603-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT71V67803
Manufacturer IDT
File Size 241.61 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet IDT71V67803 Datasheet

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Other Datasheets by IDT

Part Number Description
IDT71V67803Z 3.3V Synchronous SRAMs
IDT71V67603 3.3V Synchronous SRAMs
IDT71V67603Z 3.3V Synchronous SRAMs
IDT71V67702 (IDT71V67702 / IDT71V67902) Burst Counter Flow-Through Outputs / Single Cycle Deselect
IDT71V67703 3.3V Synchronous SRAMs

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter IDT71V67603/Z IDT71V67803/Z Pipelined Outputs, Single Cycle Deselect Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high system speed: – 166MHz 3.5ns clock access time – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) ◆ 3.3V core power supply ◆ Power down controlled by ZZ input ◆ 3.3V I/O supply (VDDQ) ◆ Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA). Description The IDT71V67603/7803 are high-speed SRAMs organized as 256K x 36/512K x 18.
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