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ICS8602 - DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

General Description

The ICS8602 is a high performance, low skew, ,&6 1-to-9 Differential-to-LVCMOS/LVTTL Zero DeHiPerClockS™ lay Buffer and a member of the HiPerClockS™ family of High Performance Clocks Solutions from ICS.

The CLK, nCLK pair can accept most standard differential input levels.

Key Features

  • Fully integrated PLL.
  • 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance.
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • Output frequency range: 15.625MHz to 250MHz.
  • Input frequency range: 15.625MHz to 250MHz.
  • VCO range: 250MHz to 500MHz.
  • External feedback for “zero delay” clock regeneration with configurable frequencies.
  • Cycle-to-cycle jitter: 36ps (typical).

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Datasheet Details

Part number ICS8602
Manufacturer Integrated Circuit Systems
File Size 143.02 KB
Description DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Datasheet download datasheet ICS8602 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY Integrated Circuit Systems, Inc. ICS8602 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR FEATURES • Fully integrated PLL • 9 LVCMOS/LVTTL outputs, 7Ω typical output impedance • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 15.625MHz to 250MHz • Input frequency range: 15.625MHz to 250MHz • VCO range: 250MHz to 500MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: 36ps (typical) • Output skew: 125ps (maximum) • Static Phase Offset: TBD±100ps (typical) • 3.