ICS671-15 Datasheet | Integrated Circuit Systems

Description The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications. The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a ZDB bank of four outputs running at 33 MHz, and two outputs at 66 MHz from the CPU PLL. This device also provides two 66 MHz zero delay clocks derived from the AGP PLL. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of the feedback clock. The ICS671-15 provides feedback clocks internally for .. the CPU PLL and the AGP PLL, and with the lowest jitter. Features - Packaged in 24-pin TSSOP - Input-output delay (±300 ps) - Two ZDB 66 MHz outputs from a 66 MHz input AGP clock - Two ZDB 66 MHz outputs, plus four 33 MHz outputs from a 33 MHz input CPU clock - Output-to-output skew is less than 250 ps - Full CMOS outputs with 18 m A output drive capability at TTL levels (at 3.3 V) - Spread Smart TM technology works with spread spectrum clock generators - Advanced, low-power, sub-micron CMOS process - Operating voltage of 3.3 V - Separate hardware output enable pins: OE1, OE2, OE3, OE4, OE5 and OE6 Block Diagram VDD 4 66M_IN 33M_IN AGP PLL OE6 66M_AGPOUT2 66M_AGPOUT1 CPU PLL OE5 66M_CPUOUT2 66M_CPUOUT1 OE4 OE3 /2 33M_PCIOUT4 OE2 33M_PCIOUT3 33M_PCIOUT2 33M_PCIOUT1 OE1 4 GND MDS 671-15 B I n t e gra te d C i r c u i t S y s t e m s - 1 525 Race Stre et, San Jo se, CA 9 5126 - Revision 021904 te l (40 8) 2 97-12 01 - w w w. i c st . c o m ICS671-15 ZERO DELAY, LOW SKEW BUFFER Pin Assignment 33M_IN VDD OE5 GND 66M_CPUOUT1 66M_CPUOUT2 VDD VDD OE3 .. 33M_PCIOUT4 33M_PCIOUT3 OE2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 66M_IN OE6 VDD 66M_AGPOUT2 66M_AGPOUT1 GND GND OE4 OE1 GND 33M_PCIOUT1 33M_PCIOUT2 24-pin (173 mil) TSSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name 33M_IN VDD OE5 GND 66M_CPUOUT1 66M_CPUOUT2 VDD VDD OE3 33M_PCIOUT4...