ICS671-15 Overview
The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications. The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a ZDB bank of four outputs running at 33 MHz, and two outputs at 66 MHz from the CPU PLL.
ICS671-15 Key Features
- Packaged in 24-pin TSSOP
- Input-output delay (±300 ps)
- Two ZDB 66 MHz outputs from a 66 MHz input AGP
- Two ZDB 66 MHz outputs, plus four 33 MHz outputs
- Output-to-output skew is less than 250 ps
- Full CMOS outputs with 18 mA output drive
- Spread SmartTM technology works with spread
- Advanced, low-power, sub-micron CMOS process
- Operating voltage of 3.3 V
- Separate hardware output enable pins: OE1, OE2
ICS671-15 Applications
- Packaged in 24-pin TSSOP