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IS61QDB22M18 - QUAD (Burst of 2) Synchronous SRAMs

Download the IS61QDB22M18 datasheet PDF. This datasheet also covers the IS61QDB21M36 variant, as both devices belong to the same quad (burst of 2) synchronous srams family and are provided as variant models within a single manufacturer datasheet.

Description

The 36Mb IS61QDB21Mx36 and IS61QDB22Mx18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

  • 1M x 36 or 2M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Separate read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with early write operation.
  • Double data rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDB21M36-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C256 32K x 8 Low Voltage CMOS STATIC RAM Integrated Silicon Solution
IS61C25616 256K x 8 High Speed CMOS STATIC RAM Integrated Silicon Solution
IS61C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDB22M18A 36Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB22M18C 36Mb QUAD Synchronous SRAM
IS61QDB22M36 QUAD (Burst of 2) Synchronous SRAMs
IS61QDB22M36A 72Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18A 18Mb QUAD (Burst 2) Synchronous SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
36 Mb (1M x 36. & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs I Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with early write operation. • Double data rate (DDR) interface for read and write input ports. • Fixed 2-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Two input clocks (C and C) for data output control. JANUARY 2010 • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.
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