Datasheet Summary
IS61QDB22M18C IS61QDB21M36C
2Mx18, 1Mx36 36Mb QUAD (Burst 2) Synchronous SRAM
MARCH 2016
Features
- 1Mx36 and 2Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with EARLY write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two output clocks (C and C#) for data output control.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously...