IS61QDB21M18A sram equivalent, 18mb quad (burst 2) synchronous sram.
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data
valid window.
* Separate independent read and write ports with
co.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
The and are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
al.
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