IS43LR16200C sdram equivalent, 1m x 16bits x 2banks mobile ddr sdram.
* JEDEC standard 1.8V power supply
* Two internal banks for concurrent operation
* MRS cycle with address key programs
- CAS latency 2, 3 (clock) - Burst leng.
where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system o.
The IS43LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture .
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