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IS42S32800 - 2M Words x 32 Bits x 4 Banks (256-Mbit) Synchronous DRAM

General Description

The ISSI IS42S32800 is a high-speed CMOS configured as a quad 2M x 32 DRAM with asynchronous interface (all signals are registered on the positive edge of the clock signal, CLK).

Each of the 2M x 32 bit banks is organized as 4096 rows by 512 columns by 32 bits.

Key Features

  • Concurrent auto precharge.
  • Clock rate:166/143 MHz.
  • Fully synchronous operation.
  • Internal pipelined architecture.
  • Four internal banks (2M x 32bit x 4bank).
  • Programmable Mode CAS# Latency: 2 or 3 Burst Length:1,2,4,8,or full page Burst Type: interleaved or linear burst Burst-Read-Single-Write.
  • Burst stop function.
  • Individual byte controlled by DQM0-3.
  • Auto Refresh and Self Refresh.
  • 409.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS42S32800 2M Words x 32 Bits x 4 Banks (256-Mbit) Synchronous DRAM P JANUARY 2008 FEATURES • Concurrent auto precharge • Clock rate:166/143 MHz • Fully synchronous operation • Internal pipelined architecture • Four internal banks (2M x 32bit x 4bank) • Programmable Mode CAS# Latency: 2 or 3 Burst Length:1,2,4,8,or full page Burst Type: interleaved or linear burst Burst-Read-Single-Write • Burst stop function • Individual byte controlled by DQM0-3 • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms (15.6µs/row) • Single +3.3V ±0.3V power supply • Interface:LVTTL • Package: 86 Pin TSOP-2,0.50mm Pin Pitch 8x13mm, 90 Ball BGA, Ball pitch 0.