HY5S2B6DLFP-SE dram equivalent, 4banks x 2m x 16bits synchronous dram.
Standard SDR Protocol Internal 4bank operation
* Voltage : VDD = 1.8V, VDDQ = 1.8V
* LVCMOS compatible I/O Interface
* Low Voltage interface to reduce I/O pow.
and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.3 / Feb. 2005 1
1HY5S2B6DLF(P)-xE 4Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION.
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