HY5DU56422LT
description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 /Oct. 2004 1
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HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T
Revision History
Revision No. History First Version Release Merged HY5DU564(8,16)22D(L)T and HY5DU564(8,16)22D(L)T-D into HY5DU564(8,16)22D(L)T. Draft Date Remark
Oct. 2004
Rev. 1.0 /Oct. 2004
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HY5DU56422D(L)T HY5DU56822D(L)T HY5DU561622D(L)T
DESCRIPTION
The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and...
