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HY5DU56422DTP - (HY5DU56x22DTP) 256M DDR SDRAM

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

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Other Datasheets by SK Hynix

Part Number Description
HY5DU56422DT (HY5DU56xx22DT) 256Mb DDR SDRAM
HY5DU56422AT (HY5DU56xx22A(L)T) 256M-S DDR SDRAM
HY5DU56422BT-D4 (HY5DU56x22BT-D4x) 256M-P DDR SDRAM
HY5DU56422BT-D43 (HY5DU56x22BT-D4x) 256M-P DDR SDRAM
HY5DU56422CF (HY5DU56xxxC(L)F) 256M DDR SDRAM

Full PDF Text Transcription

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www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP 256M DDR SDRAM HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 /May 2004 www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP DESCRIPTION PRELIMINARY The Hynix HY5DU56422D(L)TP, HY5DU56822D(L)TP and HY5DU561622(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
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