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HY5DU56422BT-D4 - (HY5DU56x22BT-D4x) 256M-P DDR SDRAM

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align D.

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HY5DU56422BT-D43 (HY5DU56x22BT-D4x) 256M-P DDR SDRAM
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HY5DU56422CF (HY5DU56xxxC(L)F) 256M DDR SDRAM
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Full PDF Text Transcription

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www.DataSheet4U.com HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 256M-P DDR SDRAM HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Revision History 1. Revision 0.2 (Jan. 2003) 1) Changed VDDmin from 2.4V to 2.5V at Page22 2) Corrected some typos. 2. Revision 0.3 (Feb. 2003) 1) IDD value update at Page 23, 24. 2) Changed some AC Paramters on AC Characteristics Table at Page27, 28. 3. Revision 0.4 (Aug. 2003) 1) Corrected some contents of Power-Up Sequence and Device Initialization.(tXSNR,tXSRD) Rev. 0.4 / Aug.
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