H5MS2622JFR Features
* SUMMARY
* Mobile DDR SDRAM clock cycle
* MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per
* Mobile DDR SDRAM INTERFACE - x32 bus width - Multiple
H5MS2532JFR_HynixSemiconductor.pdf
Datasheet Details
H5MS2622JFR, H5MS2532JFR
Hynix Semiconductor
1.57 MB
256mb (8mx32bit) mobile ddr sdram.
This datasheet PDF includes multiple part numbers: H5MS2622JFR, H5MS2532JFR.
Please refer to the document for exact specifications by model.
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H5MS2622JFR Distributor
