H57V2622GMR-60X Datasheet | SK Hynix

description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Oct. 2009 1 .. Synchronous DRAM Memory 256Mbit H57V2622GMR Series Document Title 256Mbit (8M x32) Synchronous DRAM Revision History Revision No. 0.1 1.0 History Initial Draft Release Draft Date Sep. 2009 Oct. 2009 Remark Preliminary Rev 1.0 / Oct. 2009 .. Synchronous DRAM Memory 256Mbit H57V2622GMR Series DESCRIPTION The Hynix H57V2622GMR Synchronous DRAM (Dual Die) ideally suited for the consumer memory applications which requires large memory density and high bandwidth uses Hinix’s 128Mb SDR monolithic die and has similar functionality. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x32 Input/ Output bus. All the mands are latched in synchronization with the rising edge of CLK. The Synchronous DRAM provides for programmable read or write Burst length of Programmable burst lengths: 1, 2, 4, 8 locations or full page. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The Synchronous DRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is partible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, randon-access operation. Read and write accesses to the Hynix Synchronous DRAM are burst oriented; accesses start at a selected location...