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H57V2622GMR-60X - 256Mb Dual Die Synchronous DRAM

Download the H57V2622GMR-60X datasheet PDF. This datasheet also covers the H57V2622GMR variant, as both devices belong to the same 256mb dual die synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Uses 2pcs of 128Mb Monolithic Die Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface 4096 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type Operating Temp. - Commercial Temp. : 0oC ~ 70oC, Industrial Temp. : -40oC ~ 85oC.
  • This product is in compliance with the directive pertaining of RoHS.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (H57V2622GMR_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by SK Hynix

Part Number Description
H57V2622GMR-60X 256Mb Dual Die Synchronous DRAM
H57V2622GMR-75X 256Mb Dual Die Synchronous DRAM
H57V2622GMR-75X 256Mb Dual Die Synchronous DRAM
H57V2622GMR 256Mb Dual Die Synchronous DRAM
H57V2562GFR 256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O

Full PDF Text Transcription

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www.DataSheet4U.com 256Mb : x32 Dual Die Synchronous DRAM 256M (8Mx32bit) Hynix SDRAM Memory This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Oct. 2009 1 www.DataSheet4U.com 111 Synchronous DRAM Memory 256Mbit H57V2622GMR Series Document Title 256Mbit (8M x32) Synchronous DRAM Revision History Revision No. 0.1 1.0 History Initial Draft Release Draft Date Sep. 2009 Oct. 2009 Remark Preliminary Rev 1.0 / Oct. 2009 2 www.DataSheet4U.
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