HY5MS7B2BLFP sdram equivalent, mobile ddr sdram.
SUMMARY
* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle
* Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP
www.DataS.
which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-n.
and figures Updated Status Register Rearranged pages to be more systematic Corrected editorial errors in descriptions and figures Corrected AC Input High/Low Level Voltage (VIH / VIL = 0.8*VDDQ / 0.2*VDDQ) - Updated IDD6 current - Updated tWTR in LP.
Image gallery
TAGS
Manufacturer
Related datasheet
Download (Size : 1.56MB)