SUMMARY
* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle
* Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP www.DataS.

which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-n.

and figures Updated Status Register Rearranged pages to be more systematic Corrected editorial errors in descriptions and figures Corrected AC Input High/Low Level Voltage (VIH / VIL = 0.8*VDDQ / 0.2*VDDQ) - Updated IDD6 current - Updated tWTR in LP.

HY5MS7B2BLFP

HY5-P

HY50-P

HY5002

HY5012A

HY5012W

HY50P

HY5100

HY510N

HY5116164B

HY5116164C

HY5116400B

HY5116404B

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