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HD74HC192 - Synchronous Up/Down Decade/4-bit Binary Counter(Dual Clock Line)

Description

The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter.

Both counters have two separate clock inputs, an up count input and a down count input.

Features

  • High Speed Operation: tpd (Clock Up or Count Down to Q) = 21 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 10 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC192P HD74HC193P DILP-16 pin PRDP0016AE-B.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC192 Synchronous Up/Down Decade Counter Renesas
HD74HC190 Synchronous Up/Down Decade Counter Renesas
HD74HC191 Synchronous Up/Down 4-bit Binary Counter Renesas
HD74HC193 Synchronous Up/Down 4-bit Binary Counter Renesas
HD74HC194 4-bit Bidirectional Universal Shift Register Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC190 Synchronous Up/Down Decade/4-bit Binary Counter(Single Clock Line)
HD74HC191 Synchronous Up/Down Decade/4-bit Binary Counter(Single Clock Line)
HD74HC193 Synchronous Up/Down Decade/4-bit Binary Counter(Dual Clock Line)
HD74HC194 4-bit Bidirectional Universal Shift Register
HD74HC195 4-bit Parallel-Access Shift Register

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74HC192, HD74HC193 Synchronous Up/Down Decade Counter (Dual Clock Lines) Synchronous Up/Down 4-bit Binary Counter (Dual Clock Lines) REJ03D0588-0300 Rev.3.00 Jan 31, 2006 Description The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low to high transition of either clock while the other input is held high. The direction of counting is determined by which input is clocked. These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the load input is taken low the data is loaded independently of either clock input.