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HD74HC193 - Synchronous Up/Down 4-bit Binary Counter

Download the HD74HC193 datasheet PDF (HD74HC192 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for synchronous up/down 4-bit binary counter.

Description

The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter.

Both counters have two separate clock inputs, an up count input and a down count input.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74HC192-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74HC193
Manufacturer Renesas
File Size 361.08 KB
Description Synchronous Up/Down 4-bit Binary Counter
Datasheet download datasheet HD74HC193 Datasheet

📁 Similar Datasheet

  • HD74HC193 - Synchronous Up/Down Decade/4-bit Binary Counter(Dual Clock Line) (Hitachi Semiconductor)
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  • HD74HC191 - Synchronous Up/Down Decade/4-bit Binary Counter(Single Clock Line) (Hitachi Semiconductor)
  • HD74HC192 - Synchronous Up/Down Decade/4-bit Binary Counter(Dual Clock Line) (Hitachi Semiconductor)
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Other Datasheets by Renesas
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  • HD74HC194 - 4-bit Bidirectional Universal Shift Register
  • HD74HC195 - 4-bit Parallel-Access Shift Register
  • HD74HC10 - Triple 3-input NAND Gates
  • HD74HC107 - Dual J-K Flip-Flops
  • HD74HC108 - Dual J-K Flip-Flops

Full PDF Text Transcription

Click to expand full text
HD74HC192, HD74HC193 Synchronous Up/Down Decade Counter (Dual Clock Lines) Synchronous Up/Down 4-bit Binary Counter (Dual Clock Lines) REJ03D0588-0300 Rev.3.00 Jan 31, 2006 Description The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low to high transition of either clock while the other input is held high. The direction of counting is determined by which input is clocked. These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the load input is taken low the data is loaded independently of either clock input.
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