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HD74HC191 - Synchronous Up/Down Decade/4-bit Binary Counter(Single Clock Line)

Description

The HD74HC190 and HD74HC191 are synchronous, reverside up/down counters.

The HD74HC190 is a 4-bit decade counter and the HD74HC191 is a 4-bit binary counter.

Features

  • High Speed Operation: tpd (Clock to Q) = 22 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Pin Arrangement Inputs Data B 1 QB 2 QB QA G B A CK Ripple Clock 16 VCC 15 Data A Inputs 14 Clock 13 Ripple Clock 12 Max/Min 11 Load 10 Data C 9 Data D (Top view) Inputs Outputs QA 3 Enable G 4 Inputs.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC191 Synchronous Up/Down 4-bit Binary Counter Renesas
HD74HC190 Synchronous Up/Down Decade Counter Renesas
HD74HC192 Synchronous Up/Down Decade Counter Renesas
HD74HC193 Synchronous Up/Down 4-bit Binary Counter Renesas
HD74HC194 4-bit Bidirectional Universal Shift Register Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC190 Synchronous Up/Down Decade/4-bit Binary Counter(Single Clock Line)
HD74HC192 Synchronous Up/Down Decade/4-bit Binary Counter(Dual Clock Line)
HD74HC193 Synchronous Up/Down Decade/4-bit Binary Counter(Dual Clock Line)
HD74HC194 4-bit Bidirectional Universal Shift Register
HD74HC195 4-bit Parallel-Access Shift Register

Full PDF Text Transcription

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HD74HC190/HD74HC191 Synchronous Up/Down Decade Counter (Single Clock Line) Synchronous Up/Donw 4-bit Binary Counter (Single Clock Line) Description The HD74HC190 and HD74HC191 are synchronous, reverside up/down counters. The HD74HC190 is a 4-bit decade counter and the HD74HC191 is a 4-bit binary counter. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the Enable G input is low. A high at Enable G inhibits counting.
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