* FT pin for user-configurable flow through or pipeline operation
* Dual Cycle Deselect (DCD) operation
* IEEE 1149.1 JTAG-compatible Boundary Scan
* 1.8 .

* JEDEC-standard 165-bump FP-BGA package
* Pb-Free 165-bump BGA package available Functional Description Applica.

Applications The GS8321EV18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache appli.

GS8321EV36GE

GS8321EV32E

GS8321EV32GE

GS8321EV18E

GS8321EV18GE

GS8321E18E

GS8321E18E-V

GS8321E18GE

GS8321E18GE-V

GS8321E32E

GS8321E32E-V

GS8321E32GE

GS8321E32GE-V

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