Description
Address Address Address Advance Clock Echo Clock Echo Clock Data I/O Type Input Input Input Input Input Output Output Input/Output Comments - x18 version only x18 and x36 versions Active High Active High Active High Active Low x18 and x36 versions DQ E1 E2 & E3 EP2 & EP3 TCK TDI TDO TMS MCH MCL MCL Data I/O Chip Enable www.DataSheet.co.kr Input/Output Input Input Input Input Input Output Input Input Input Input x36 version Active Low Programmable Active High or Low - Active High - - - Active High (all versions) Active Low (all versions) Active Low (x36 version) Chip Enable Chip Enable Program Pin Test Clock Test Data In Test Data Out Test Mode Select Must Connect High Must Connect Low Must Connect Low 4/31 © 2002, GSI Technology, Inc. Specifications cited are design targets and are subject to change without notice.
Key Features
- Double Data Rate Read and Write mode
- JEDEC-standard SigmaRAM™ pinout and package
- 1.8 V +150/-100 mV core power supply
- 1.5 V or 1.8 V I/O supply
- Pipelined read operation
- Fully coherent read and write pipelines
- Echo Clock outputs track data output drivers
- ZQ mode pin for user-selectable output drive strength
- 2 user-programmable chip enable inputs for easy depth expansion
- IEEE 1149.1 JTAG-compatible Boundary Scan
