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Fairchild Semiconductor Electronic Components Datasheet

DM74AS648 Datasheet

Octal Bus Transceiver and Register

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October 1986
Revised July 2003
DM74AS646 DM74AS648
Octal Bus Transceiver and Register
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal register to
bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance third
state and increased high-logic-level drive provide this
device with the capability of being connected directly to and
driving the bus lines in a bus-organized system without
need for interface or pull-up components. It is particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74AS646, DM74AS648 are edge-
triggered D-type flip-flops. On the positive transition of the
clock (CAB or CBA), the input bus data is stored.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects
stored data. The select controls have a “make before
break” configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between stored and real-time data.
The enable G and direction control pins provide four modes
of operation; real-time data transfer from bus A to B, real-
time data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internal store data
transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.
Features
s Switching specifications at 50 pF
s Switching specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with LS TTL
counterpart
s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:
Order Number Package Number
Package Description
DM74AS646WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
DM74AS646NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DM74AS648WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
DM74AS648NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2003 Fairchild Semiconductor Corporation DS006324
www.fairchildsemi.com


Fairchild Semiconductor Electronic Components Datasheet

DM74AS648 Datasheet

Octal Bus Transceiver and Register

No Preview Available !

Connection Diagram
Function Table
Inputs
Data I/O (Note 1)
Operation or Function
G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8
DM74AS646
H X H or L H or L X X
Input
Input Isolation, Hold Storage
X
XX
Store A and B Data
DM74AS648
Isolation, Hold Storage
Store A and B Data
LL
L
X XX
X H or L X
L
H
Output
Input
Real Time B Data to A Bus Real Time B Data to A Bus
Stored B Data to A Bus Stored B Data to A Bus
LH X
X LX
Input
Output Real Time A Data to B Bus Real Time A Data to B Bus
H H or L X H X
Stored A Data to B Bus Stored A Data to B Bus
X X X X X Input Unspecified Store A, B Unspecified Store A, B Unspecified
(Note 1)
(Note 1)
(Note 1)
X X X X X Unspecified Input Store B, A Unspecified Store B, A Unspecified
(Note 1)
(Note 1)
(Note 1)
HHIGH level; LLOW level; Xirrelevant; LOW-to-HIGH level transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
www.fairchildsemi.com
2


Part Number DM74AS648
Description Octal Bus Transceiver and Register
Maker Fairchild Semiconductor
Total Page 8 Pages
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