74ALVCH16244 Datasheet | Fairchild Semiconductor

Description The ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble (4-bit) controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16244 is designed for low voltage (1.65V to 3.6V) VCC applications with output capability up to 3.6V. The 74ALVCH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. Features s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminating the need for external pull-up/pull-down resistors s t PD 3 ns max for 3.0V to 3.6V VCC 3.7 ns max for 2.3V to 2.7V VCC 6.0 ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V Ordering Code: Order Number 74ALVCH16244T Package Number MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn I0- I15 O0- O15 Description Output Enable Input (Active LOW) Bushold Inputs Outputs © 2002 Fairchild Semiconductor Corporation DS500625 .fairchildsemi. Connection Diagram Truth Tables Inputs OE1 L L H Inputs OE3 L L H Inputs OE2 L L H Inputs OE4 L L H I12-I15 L H X I4-I7 L H X I8-I11 L H X I0- I3 L H X Outputs O0- O3 L H Z Outputs O8- O11 L H Z Outputs O4-O7 L H Z Outputs O12-O15 L H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not...