EM42AM1684RTC Datasheet | Eorex

Revision History Revision 0.1 (Jul. 2010) - First release. Revision 0.2 (Sep. 2010) - Delete CL=2, page 2, 8, 17 - Add 166MHz@2.5-3-3; 200MHz@3-3-3, page 2 EM42AM1684RTC Sep. 2010 .eorex. 1/21 EM42AM1684RTC 256Mb (4M×4Bank×16) Double DATA RATE SDRAM Features Description - Internal Double-Date-Rate architecture with twice accesses per clock cycle. - Single 2.5V ±0.2V Power Supply - 2.5V SSTL-2 patible I/O - Burst Length (B/L) of 2, 4, 8 - 2.5, 3 clock read latency - Bi-directional, intermittent data strobe (DQS) - All inputs except data and DM are sampled at the positive edge of the system clock. - Data Mask (DM) for write data - Sequential & Interleaved Burst type available - Auto precharge option for each burst accesses - DQS edge-aligned with data for Read cycles - DQS center-aligned with data for Write cycles - DLL aligns DQ & DQS transitions with CLK transition - Auto Refresh and Self Refresh - 8,192 Refresh Cycles / 64ms The EM42AM1684RTC is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Meg words x 4 banks by 16 bits. The 256Mb DDR SDRAM uses a double data rate architecture to acplish high-speed operation. The data path internally prefetches multiple bits and transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I/O pins. Available package: TSOPII 66P 400mil. Ordering Information...