74AUP2G04 Datasheet | Diodes Incorporated

Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G04 is posed of two inverters with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. The gates perform the positive Boolean function: YA Features - Advanced Ultra Low Power (AUP) CMOS - Supply Voltage Range from 0.8V to 3.6V - ± 4m A Output Drive at 3.0V - Low Static Power Consumption - ICC < 0.9µA - Low Dynamic Power Consumption - CPD = 4p F Typical at 3.6V - Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for Slower Input Rise and Fall Time. The Hysteresis is Typically 250m V at VCC = 3.0V - IOFF Supports Partial-Power-Down Mode Operation - ESD Protection per JESD 22 - Exceeds 200-V Machine...