S26KL512S devices equivalent, high-speed cmos mirrorbit nor flash devices.
* 3.0V I/O, 11 bus signals
* Single ended clock
* 1.8V I/O, 12 bus signals
* Differential clock (CK, CK#)
* Chip Select (CS#)
* 8-bit data bus (DQ.
. 4 1.1 DDR Center Aligned Read Strobe
Functionality (DCARS) ......... 6 1.2 Error Detection and Correction Functionality...... 6
2. Connection Diagram. 9 2.1 FBGA 24-Ball 5 x 5 Array Footprint 9
3. Signal Description .. 10
4. HyperBus Protocol . 11.
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