S26KL512S flash equivalent, 512mb (64mb) hyper flash.
* 3.0 V I/O, 11 bus signals - Single ended clock
* 1.8 V I/O, 12 bus signals - Differential clock (CK, CK#)
* Chip Select (CS#)
* 8-bit data bus (DQ[7:0]).
5 1.1 DDR center aligned read strobe (DCARS) functionality ........7 1.2 Error detection and correction functionality ....7 2 Connection diagram........10 2.1 FBGA 24-ball 5 × 5 array footprint 10 3 Signal description .11 4 HYPERBUS™ protocol ......1.
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