CY7C1525AV18
Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 250 MHz clock for high bandwidth
- 2-word burst on all accesses
- Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high-speed systems
- Single multiplexed address input bus latches address inputs for both read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
- QDR-II operates with 1.5 cycle read latency when Delay Lock Loop (DLL) is enabled
- Operates as a QDR-I device with 1 cycle read latency in DLL off mode
- Available in x 8, x 9, x 18, and x 36 configurations
- Full data coherency, providing most current data
- Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to...
