CY7C1510AV18, CwYww7.DCat1a5Sh2ee5t4AU.Vco1m8
CY7C1512AV18, CY7C1514AV18
72-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 250 MHz clock for high bandwidth
■ 2-word burst on all accesses
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 500 MHz) at 250 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
■ Operates as a QDR-I device with 1 cycle read latency in DLL
off mode
■ Available in x 8, x 9, x 18, and x 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
250 MHz
250
1230
1240
1350
1560
Configurations
CY7C1510AV18 – 8M x 8
CY7C1525AV18 – 8M x 9
CY7C1512AV18 – 4M x 18
CY7C1514AV18 – 2M x 36
Functional Description
The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and
CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II architecture. QDR-II architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR-II archi-
tecture has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus that exists with
common IO devices. Access to each port is through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR-II read and write ports are completely independent
of one another. To maximize data throughput, both read and write
ports are equipped with DDR interfaces. Each address location
is associated with two 8-bit words (CY7C1510AV18), 9-bit words
(CY7C1525AV18), 18-bit words (CY7C1512AV18), or 36-bit
words (CY7C1514AV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turn-arounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
200 MHz
200
1005
1015
1105
1280
167 MHz
167
850
860
935
1090
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06984 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 27, 2007
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