Datasheet4U Logo Datasheet4U.com

CY7C1525KV18 - 72-Mbit QDR II SRAM Two-Word Burst Architecture

Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 350 MHz clock for high bandwidth.
  • Two-word burst on all accesses.
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
  • Echo clocks (CQ and CQ) sim.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CY7C1520AV18 72-Mbit DDR-II SRAM Cypress
CY7C1518AV18 72-Mbit DDR-II SRAM Cypress
CY7C1006D 1-Mbit (256K x 4) Static RAM Cypress
CY7C1011G 2-Mbit (128K words x 16 bit) Static RAM Cypress
CY7C1041G 4-Mbit (256K words x 16 bit) Static RAM Cypress

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1525AV18 72-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1525V18 1.8V Synchronous Pipelined SRAM
CY7C1520KV18 72-Mbit DDR-II SRAM Two-Word Burst Architecture
CY7C1520V18 1.8V Synchronous Pipelined SRAM
CY7C1521KV18 72-Mbit DDR II SRAM Four-Word Burst Architecture

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR® II SRAM Two-Word Burst Architecture 72-Mbit QDR® II SRAM Two-Word Burst Architecture Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 350 MHz clock for high bandwidth ■ Two-word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write ports (data transferred at 700 MHz) at 350 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed systems ■ Single multiplexed address input bus latches address inputs for both read and write ports ■ Separate port selects for depth expansion ■ Synchronou
Published: |