CY7C1475V25 Overview
The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
CY7C1475V25 Key Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Can support up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte Write capability
- 2.5V/1.8V I/O power supply
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)