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CY7C1475V33 - (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

Download the CY7C1475V33 datasheet PDF. This datasheet also covers the CY7C1473V33 variant, as both devices belong to the same (cy7c147xv33) 72-mbit (2m x 36/4m x 18/1m x 72) flow-through sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states.

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133 MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte Write capability.
  • 3.3V/2.5V IO supply (VDDQ).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1473V33_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1475V25 (CY7C147xV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C147 4K x 1 STATIC RAM
CY7C1470BV25 (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1470BV33 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
CY7C1470V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self timed output buffer control to eliminate the need to use OE • Registered inputs for flow through operation • Byte Write capability • 3.3V/2.5V IO supply (VDDQ) • Fast clock-to-output times — 6.
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