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Cypress Semiconductor Electronic Components Datasheet

CY7C1474V25 Datasheet

72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM

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CY7C1470V25
CY7C1472V25
CY7C1474V25
72-Mbit (2M × 36/4M × 18/1M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 200-MHz bus operations with zero wait states
Available speed grades are 200 and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 2.5 V power supply
2.5 V I/O supply (VDDQ)
Fast clock-to-output times
3.0 ns (for 200-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1470V25 available in JEDEC-standard Pb-free 100-pin
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
CY7C1472V25 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1474V25 available in Pb-free and non Pb-free
209-ball FBGA package
IEEE 1149.1 JTAG boundary scan compatible
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V,
2M × 36/4M × 18/1M × 72 synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible
and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1474V25, BWa–BWd for CY7C1470V25
and BWa–BWb for CY7C1472V25) and a write enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
200 MHz
3.0
450
120
167 MHz
3.4
400
120
Unit
ns
mA
mA
Errata: For information on silicon errata, see Errata on page 36. Details include trigger conditions, devices affected, and proposed workaround
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05290 Rev. *V
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 4, 2018


Cypress Semiconductor Electronic Components Datasheet

CY7C1474V25 Datasheet

72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM

No Preview Available !

CY7C1470V25
CY7C1472V25
CY7C1474V25
Logic Block Diagram – CY7C1470V25
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BWa
BWb
BWc
BWd
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Document Number: 38-05290 Rev. *V
Page 2 of 41


Part Number CY7C1474V25
Description 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM
Maker Cypress Semiconductor
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