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CY7C1474BV25 - (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM

Download the CY7C1474BV25 datasheet PDF. This datasheet also covers the CY7C1470BV25 variant, as both devices belong to the same (cy7c147xbv25) 72-mbit (2m x 36/4m x 18/1m x 72) pipelined sram family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back read or write operations with no wait states.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1470BV25_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1474BV33 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM
CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C1474V33 (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
CY7C147 4K x 1 STATIC RAM
CY7C1470BV25 (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM

Full PDF Text Transcription

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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions.
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