CY7C1473V33
Overview
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Supports up to 133 MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin compatible and functionally equivalent to ZBT™ devices
- Internally self timed output buffer control to eliminate the need to use OE
- Registered inputs for flow through operation
- Byte Write capability
- 3.3V/2.5V IO supply (VDDQ)
- Fast clock-to-output times - 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
