CY7C1473V33
Features
- No Bus Latency™ (No BL™) architecture eliminates dead cycles between write and read cycles
- Supports up to 133 MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self timed output buffer control to eliminate the need to use OE
- Registered inputs for flow through operation
- Byte Write capability
- 3.3V/2.5V IO supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self timed writes
- Asynchronous Output Enable (OE)
- CY7C1471V33, CY7C1473V33 available in JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and non-Pb-free 165-Ball FBGA package. CY7C1475V33 available in Pb-free and non-Pb-free 209-Ball FBGA package
- Three Chip Enables (CE1, CE2, CE3) for simple depth expansion
- Automatic power down feature available using ZZ mode or CE deselect
- IEEE 1149.1 JTAG Boundary Scan patible
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