CY7C1424AV18 architecture equivalent, 36-mbit ddr-ii sio sram 2-word burst architecture.
* 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
* 300-MHz clock for high bandwidth
* 2-Word burst for reducing address bus frequency
* Double Data Ra.
The CY7C1422V18, CY7C1429AV18, CY7C1423V18, CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read por.
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