CY7C142 Datasheet

Manufacturer: Cypress (now Infineon)

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Two ports are provided to permit independent access to any location in memory. The CY7C132, CY7C136,.

True dual-ported memory cells that enable simultaneous reads of the same memory location
2K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: ICC = 110 mA (maximum)
Fully asynchronous operation
Automatic power-down
Master CY7C132/CY7C136/CY7C136A[1] easily expands data
BUSY output flag on CY7C132/CY7C136/CY7C136A; BUSY input on CY7C142/CY7C146
INT flag for port to port munication (52-Pin PLCC/PQFP versions)

Part Number	Description
CY7C1420AV18	(CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420BV18	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420JV18	36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1420KV18	36-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1421AV18	1.8V Synchronous Pipelined SRAM
CY7C1422AV18	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422BV18	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1422JV18	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1423AV18	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1423BV18	36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture