Datasheet4U Logo Datasheet4U.com

CY7C1423BV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

This page provides the datasheet information for the CY7C1423BV18, a member of the CY7C1422BV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture family.

Description

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture.

The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Functional.

📥 Download Datasheet

Datasheet preview – CY7C1423BV18

Datasheet Details

Part number CY7C1423BV18
Manufacturer Cypress Semiconductor
File Size 711.61 KB
Description 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Datasheet download datasheet CY7C1423BV18 Datasheet
Additional preview pages of the CY7C1423BV18 datasheet.

📁 Similar Datasheet

  • CY7C1460SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress)
  • CY7C1462SV25 - 36-Mbit (1M x 36/2M x 18) Pipelined SRAM (Cypress)
  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1423AV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
  • CY7C1423JV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
  • CY7C1423KV18 - 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
  • CY7C142 - 2K x 8 Dual-Port Static RAM
  • CY7C1420AV18 - (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1420BV18 - 36-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1420JV18 - 36-Mbit DDR-II SRAM 2-Word Burst Architecture
  • CY7C1420KV18 - 36-Mbit DDR II SRAM Two-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus.
Published: |