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CY7C1423JV18 - 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Download the CY7C1423JV18 datasheet PDF. This datasheet also covers the CY7C1422JV18 variant, as both devices belong to the same 36-mbit ddr-ii sio sram 2-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Description

The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and CY7C1424JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture.

The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1422JV18_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C1423AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1423BV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1423KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
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Full PDF Text Transcription

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CY7C1422JV18, CY7C1429JV18 CY7C1423JV18, CY7C1424JV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1422JV18, CY7C1429JV18, CY7C1423JV18, and CY7C1424JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.
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