* 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
* 300-MHz clock for high bandwidth
* 4-Word burst for reducing address bus frequency
* Double Data Ra.

CY7C141

CY7C1410AV18

CY7C1410JV18

CY7C1410V18

CY7C1411AV18

CY7C1411BV18

CY7C1411JV18

CY7C1411KV18

CY7C1412AV18

CY7C1412JV18

CY7C1412KV18

CY7C1412V18

CY7C1413AV18

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