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CY7C1415BV18 - (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Download the CY7C1415BV18datasheet PDF (CY7C1413BV18 included). The datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications.

Description

The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and CY7C1415BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

Features

  • Configurations CY7C1411BV18.
  • 4M x 8 CY7C1426BV18.
  • 4M x 9 CY7C1413BV18.
  • 2M x 18 CY7C1415BV18.
  • 1M x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.

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Datasheet preview – CY7C1415BV18

Datasheet Details

Part number CY7C1415BV18
Manufacturer Cypress (now Infineon)
File Size 757.79 KB
Description (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet download datasheet CY7C1415BV18 Datasheet
Additional preview pages of the CY7C1415BV18 datasheet.

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Full PDF Text Transcription

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